This invention relates generally to semiconductor electrically erasable programmable read only memories (EEPROM) and specifically to techniques for optimum erasing and programming of them.
Computer systems typically use magnetic disk drives for mass storage of data. However, disk drives are disadvantageous in that they are bulky and in their requirement for high precision moving mechanical parts. Consequently, they are not rugged and are prone to reliability problems as well as consuming significant amounts of power. Solid state memory devices such as DRAM's and SRAM's do not suffer from these disadvantages. However, they are much more expensive and require constant power to maintain their memory (volatile). Consequently, they are typically used as temporary storage.
ROM, EEPROM and Flash EEPROM are all non-volatile solid state memories. They retain their memory even after power is shut down. However, ROM and PROM cannot be reprogrammed. UVPROM cannot be erased electrically. On the other hand, EEPROM and Flash EEPROM have the further advantage of being electrically writable (or programmable) and erasable.
Nevertheless, conventional EEPROM and Flash EEPROM have a limited lifetime due to the endurance-related stress the device suffers each time it goes through an erase/program cycle. The endurance of a Flash EEPROM device is its ability to withstand a given number of program/erase cycles. Thus, with use, defects tend to build up in the memory array and typically the devices are rendered unreliable after 10.sup.3 to 10.sup.4 write/erase cycles.
It is desirable to have a specific type of semiconductor memory system having non-volatility, ease of erasing and rewriting, speed of access, low cost and reliability.
The program/erase operation cycle is the single most stressful operation on EEPROM. Furthermore, it is also the most time-consuming operation. Traditionally, EEPROM and Flash EEPROM are used in applications where semi-permanent storage of data or program is required but with a limited need for reprogramming.
Optimized erase implementations for EEPROM systems have been disclosed in several copending U.S. patent applications. U.S. patent application Ser. No. 204,175, now U.S. Pat. No. 5,095,344, filed Jun. 8, 1988, by Dr. Eliyahou Harari, discloses an intelligent erase method for improved endurance. The flash EEPROM cells are erased by applying a pulse of erasing voltage followed by a read operation to verify if the cells are erased to the "erased" state. If not, further pulsing and verifying are repeated until the cells are verified to be erased. By erasing in this controlled manner the cells are not subjected to over-stress or over-erasure. Over-erasure tends to age the EEPROM device prematurely as well as to make the cells harder to re-program. Co-pending U.S. patent application Ser. No. 337,566, filed Apr. 13, 1989, by Dr. Eliyahou Harari et al., discloses selective-multiple-sector erase, in which any combination of flash sectors may be erased together. Those sectors that have been verified as erased are removed from further pulses of erasing voltage, thereby preventing them from over-erasing.
The various techniques disclosed are generally associated with a set of erase parameters which is optimized for the EEPROM for a given juncture in its history. As the EEPROM is subjected to program/erase cycling through use, the erase parameters tend to deviate from their optimum values.
While the incremental pulsing method helps reduce stress, further improvements are possible to minimize stress without sacrificing performance.
Accordingly, it is a primary object of the present invention to provide techniques for improving the performance of erasing and programming of EEPROM system while minimizing stress and maximizing performance.
It is another object of the present invention to provide techniques for maintaining optimum erase parameters during the history of the EEPROM program/erase cycling.